Aktuelle Senior Project Manager Drink Systems Mwd Jobs in Oberderdingen

Die BLANC & FISCHER Corporate Services übernimmt als konzernübergreifende Einheit eine übergeordnete Steuerungsfunktion und zentrale Dienstleistungen für die Unternehmen der BLANC & FISCHER Familienholding. Die rund 300 Spezialisten decken dabei 14...

Erfolgsprämien; Fahrradfreundlich; Firmenfahrrad; Fitness; Flexible Arbeitszeiten; Home-Office möglich; Kantine; Monetäre Leistungen; Prämien; Sonderzahlungen; Sportangebote; Verpflegung; Work-Life-Balance

Technical Proficiency: Azure Logic Apps: Experience in designing and implementing workflows using Azure Logic Apps. Azure Service Bus: Proficiency in setting up and managing Azure Service Bus for messaging and communication between applications. Azure API Management: Knowledge of configuring and man

University degree, Diploma or BS EE Background in digital design (SOC), Application Specific Integrated Circuit (ASIC) design methodologies and silicon development cycle Experience in Register Transfer Level (RTL) coding (Verilog) Experience with standard simulation tools for digital designs Basic k

University degree, Diploma or MS EE Background in analog and full custom design (SOC) Application Specific Integrated Circuit (ASIC) design methodologies and silicon development cycle Experience with modern leading edge CMOS processes Experience with standard simulation tools for analog designs Know

Firmenkultur; Flache Hierarchien; Keine Home-Office Angabe

Firmenkultur; Flache Hierarchien; Keine Home-Office Angabe

BS in Electrical Engineering/Physics/Computer Science or equivalent with over 5 years semiconductor test experience. Strong device- and test-program coding and debugging skills in V93k SMT8 and smart RDI Knowledge of digital, mixed signal, RF and power device test methodologies Ability to quickly pi

University degree, Diploma or BS EE Background in digital design (SOC), Application Specific Integrated Circuit (ASIC) design methodologies and silicon development cycle Experience in Register Transfer Level (RTL) coding (Verilog and System Verilog) Experience with standard simulation tools for digi

University degree, Diploma or BS EE Background in digital design (SOC), ASIC design methodologies and silicon development cycle Experience in Register Transfer Level (RTL) coding (Verilog and System-Verilog) Experience with verification methodologies and concepts Experience with standard simulation